The initial models retain the Clovertown 1333MHz front side bus (a higher 1600Mhz FSB model expected next year). With Intel Smart Cache, the Level 2 cache has been increased to a healthy 12MB (2x6MB shared L2 for each set of cores).

On mainstream processor models the Total Dissipated Power (TDP) rating remains at 80W but there will be some low power variations also released next year and an extreme model at 120W (the one with 1600FSB) also coming out later.

The server board socket type (LGA 771) has not changed, but not all existing motherboards will support these CPU so careful attention must be paid when purchasing components. (NOTE: Existing Bensley platform products - 5000 chipset - are being refreshed to support these processors. New SKU will be available on certain products). Next year Intel will launch a new server chipset 5100 San Clemente that will also support these processors. Harpertown is designed to ultimately replace the current 65nm, quad-core Clovertown (5300-series) line.

Key New Technologies:

Core Microarchitecture Optimizations: Increases the overall performance and energy efficiency of the already leading Intel Core microarchitecture to deliver more instruction executions per clock cycle, which results in more performance and better system responsiveness.

High-K Process Technology: In order to extend Moore's Law, Intel uses a new material in their transistors which is a combination of high-k gate dielectrics and metal gates. This new technology increases the switching speed of the transistors and helps reduce power consumption to allow Intel to continue to deliver faster processors that consume less power.

New SSE4 Instructions: Harpertown includes Intel Streaming SIMD Extensions 4 (SSE4) instructions, the largest unique instruction set addition since the original SSE (47 new instructions) including video accelerators and much more. This extends the Intel 64 instruction set architecture to expand the performance and capabilities of the Intel Architecture.

Unique Super Shuffle Engine: By implementing a full-width, single-pass shuffle unit that is 128-bits wide, Penryn processors can perform full-width shuffles in a single cycle. This significantly improves performance for SSE2, SSE3 and SSE4 instructions that have shuffle-like operations such as pack, unpack and wider packed shifts. This feature will increase performance for content creation, imaging, video and high-performance computing.

5400 Processor Model Chart

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